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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD6435 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1997 adsl chipset functional block diagram bypass port elastic store, framing, byteCstuff/rob digital logic, fec, crc interleaving receive control to adtsp2183 duplex_tx duplex_rx simplex_tx (atu-c) simplex_rx (atu-r) interleave ram to ad6436/ad6439 from ad6436/ad6439 AD6435 transmit features component in analog devices dmt adsl chipset ad20msp910 designed to ansi/etsi t1.413 suitable for co or residence (atu-r and atu-c) performs all digital interface tasks: elastic store; byte-stuffing/robbing synch ronization and eoc and aoc insertion/removal crc generation/detection scrambler and descrambler forward error correction/detection interleave/deinterleave absolute maximum data rate: 12 mbps simplex/ 4 mbps duplex simple interface: synchronous simplex and duplex streams 128-lead tqfp operating temperature range: C40 8 c to +85 8 c 3.3 v operation, 400 mw general description the AD6435 is part of the analog devices adsl chipset, the ad20msp910. it accompanies the ad6436 (dmt accelerator), ad6437 (single-chip analog front end) and adtsp-2183 (con- trol and dsp). object code is also supplied. offering a flex- ible, standard-based approach (designed to ansi t1.413, category 1) with low total bill of ma terials and high perfor- mance, the chipset offers a straightforward approach to realizing an adsl modem. the AD6435 interfaces the adsl modem to the external sys- tem, at either co or rt modem. it implements all the bit- stuffing/robbing and elastic store operations, and all digital processing (block and forward error correction, scrambling, interl eaving, etc.). the AD6435 has four simple synchronous connections, duplex in and out, simplex in (only used at atu-c) and simplex out (used at atu-r), which may be treated as the as0 simplex and ls0 duplex stream of the stan- dard. these have clean clock and data, and may operate asynchronously of one another, or of the modem itself.
C2C rev. 0 AD6435Cspecifications parameter units comments absolute maximum simplex data rate 12.288 mbps absolute maximum. may not be achieved under realistic conditions. actual performance will depend on copper loop. absolute maximum duplex data rate 4.096 mbps absolute maximum. may not be achieved under realistic conditions. actual performance will depend on copper loop. internal pll for clock regeneration 176.64 mhz resolution is 172.5 hz/bit 0.076 unit intervals. v dd supply voltage 3.3 v 10% power dissipation 400 mw typical t a operating temperature C40 c to +85 c specifications are subject to change without notice. absolute maximum ratings * supply voltage . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +4.6 v input voltage . . . . . . . . . . . . . . . . . . . . C0.5 v to v dd + 0.5 v output voltage swing . . . . . . . . . . . . . C0.5 v to v dd + 0.5 v operating temperature range (ambient) . . . C40 c to +85 c storage temperature range . . . . . . . . . . . . C65 c to +150 c lead temperature (5 sec) tqfp . . . . . . . . . . . . . . . . +280 c *stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD6435 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device electrical specifications parameter typ value comments* v oh v dd C0.4 v dc at i oh = C0.5 ma v ol 0.4 v dc at i ol = +1.0 ma v ih 2.0 v dc v il 1.0 v dc i ih 500 na v in = v dd = 3.6 v i il 500 na v in = 0 v, v dd = 3.6 v *v dd = 3.3 v dc 10%. ordering guide model temperature range package description package option AD6435 C40 c to +85 c 128-lead plastic thin quad flatpack st-128
AD6435 C3C rev. 0 pin configuration vdd14 gnd14 d4 d5 d6 d8 d9 d10 d11 gnd13 vdd13 d12 d13 d14 d15 nreset nwr d2 d3 d7 nrd ncs gnd12 vdd12 a0 a1 a2 a3 a4 a5 a6 a7 nc nc pll_gnd pll_vdd pll_rbias nc vdd11 test3 gnd11 vdd5 dsp_clk gnd5 a8 m_d7 a9 m_d6 a10 m_d5 a11 m_d4 a12 m_d3 vdd10 m_d2 gnd10 m_d1 a13 m_d0 rx_frm vdd6 rx_sdata gnd6 mclk nm_oe gnd8 vdd8 nm_we m_a14 m_a13 m_a12 d1 d0 test4 simplx_tx simplx_clk i simplx_clko vdd1 gnd1 simplx_rx duplx_tx duplx_clki duplx_clko duplx_rx rx_buf vdd2 gnd2 rfs rx_fr rx_spfr rx_spfri tx_buf tfs gnd3 vdd3 tx_fr tx_spfr mclk_out test0 test1 rt_nco gnd4 vdd4 m_a11 m_a10 rx_dreq rx_bs tx_rx_sclk gnd9 vdd9 tx_frm m_a0 m_a1 m_a2 m_a3 m_a4 m_a5 m_a6 m_a7 gnd7 vdd7 m_a8 m_a9 tx_sdata tx_bs tx_dreq test2 nc = no connect 92 93 95 90 91 88 89 87 96 86 94 81 82 83 84 79 80 78 76 77 85 75 73 74 71 72 69 70 67 68 66 65 98 99 101 97 102 10 0 41 42 43 44 46 47 48 49 39 45 40 62 61 60 64 63 59 55 50 51 52 53 54 56 57 58 11 10 16 15 14 13 18 17 20 19 22 21 12 24 23 26 25 28 27 30 29 32 31 5 4 3 2 7 6 9 8 1 34 33 36 35 38 37 120 121 122 123 124 125 126 127 128 119 111 118 117 116 115 114 113 112 110 109 108 107 106 105 104 103 pin 1 identifier top view (not to scale) AD6435 dtir 128 tqfp
AD6435 C4C rev. 0 pin function descriptions pin no. pin name type description 1C2 d1, d0 i/o 16-bit data bus for dsp port. see also 111:114, 117:124, 127:128. 3 test4 input tie to ground through a 10 k w resistor. 4 simplx_tx input input downstream data at co. pin not used at rt. 5 simplx_clki input input clock at co for downstream data. pin is not used at rt. 6 simplx_clko output recovered downstream clock at rt. pin not used at co. 7 vdd1 supply 3.3 v. 8 gnd1 supply ground. 9 simplx_rx output received downstream data at rt. pin not used at co. 10 duplx_tx input input duplex data. 11 duplx_clki input input duplex clock. 12 duplx_clko output recovered duplex clock. 13 duplx_rx output received duplex data stream. 14 rx_buf output ticl bypassrx data buffer. if tcil is not used, this pin must have a pull-up resistor. 15 vdd2 supply 3.3 v. 16 gnd2 supply ground. 17 rfs output ticl bypassrx byte sync. 18 rx_fr output ticl bypassrx frame sync. 10 k w to ground. 19 rx_spfr output ticl bypassticl superframe sync. 20 rx_spfri output ticl bypassrx interleaved superframe sync. 21 tx_buf input ticl bypasstx data buffer. 22 tfs output ticl bypasstx byte sync. 23 gnd3 supply ground. 24 vdd3 supply 3.3 v. 25 tx_fr output ticl bypasstx frame sync. 26 tx_spfr output ticl bypasstx superframe sync. 27 mclk_out output ticl bypassoutput mclk. 28 test0 no connection. 29 test1 no connection. 30 rt_nco mode pin, 1 = rt mode, 0 = co mode. 31 gnd4 supply ground. 32 vdd4 supply 3.3 v. 33, 34 nc no connect. 35 pll_gnd pll analog ground. 36 pll_vdd pll analog power. 37 pll_rbias tie to ground through a 30 k w resistor. 38 nc no connect. 39 test2 input tie to ground through a 10 k w resistor. 40 test3 three-state no connection. 41 vdd5 supply 3.3 v. 42 gnd5 supply ground. 43C50 m_d7C0 i/o data for interleave ram. 51 vdd6 supply 3.3 v. 52 gnd6 supply ground. 53C60 m_a0C7 output address bus for interleave ram. see also pins 60C66. pin description the AD6435 contains 91 signal pins, 33 output pins, 35 input pins, and 24 bidirectional pins. there are also 5 test pins and 28 digital supply pins, 2 analog supply pins, and 1 pll bias pin for the pll.
AD6435 C5C rev. 0 pin function descriptions (continued) pin no. pin name type description 61 gnd7 supply ground. 62 vdd6 supply 3.3 v. 63C69 m_a8C14 output address bus for interleave ram. see also pins 50C57. 70 nm_we output write enable for interleave ram. 71 vdd8 supply 3.3 v. 72 gnd8 supply ground. 73 nm_oe output output enable for interleave ram. 74 mclk input the AD6435 master clk (35.328 mhz). 75 tx _dreq input data request provided by the ad6436. 76 tx _bs output transmit byte strobe provided by the AD6435. 77 tx _sdata output transmit serial data provided by the AD6435. 78 tx _frm input transmit frame strobe provided by the ad6436. 79 vdd9 supply 3.3 v. 80 gnd9 supply ground. 81 tx _rx_sclk input transmit and receive serial clock. 82 rx_bs input receive byte strobe provided by the ad6436. 83 rx_dreq output receive data request provided by the AD6435. 84 rx_sdata input receive serial data provided by the ad6436. 85 rx_frm input receive frame strobe provided by the ad6436. 86 a13 input 14-bit address bus for dsp port. see also 86C90 and 94C101. 87 gnd10 supply ground. 88 vdd10 supply 3.3 v. 89C93 a12Ca8 input 14-bit address bus for dsp port. see also 83 and 94C101. 94 dsp_clk input dsp output clock. 95 gnd11 supply ground. 96 vdd11 supply 3.3 v. 97C104 a7C0 supply 14-bit address bus for dsp port. see also 83 and 86C90. 105 vdd12 supply 3.3 v. 106 gnd12 supply ground. 107 ncs input dsp memory select. active low. 108 nrd input dsp memory read enable, active low. 109 nwr input dsp write enable, active low. 110 nreset input reset pin, active low. 111C114 d15Cd12 i/o 16-bit data bus for dsp port. see also 1C2, 117C124, 127C128. 115 vdd13 supply 3.3 v. 116 gnd13 supply ground. 117C124 d11Cd4 i/o 16-bit data bus for dsp port. see also 1C2, 111C114, 127C128. 125 gnd14 supply ground. 126 vdd14 supply 3.3 v. 127, 128 d3Cd2 i/o 16-bit data bus for dsp port. see also 1C2, 111C114, 117C124.
AD6435 C6C rev. 0 introduction the AD6435 is the interface chip in the ad20msp910 adsl chipset, connecting the core transceiver functions to the external system. the other portions within the ad20msp910 chipset are the ad6436 (which connects to the AD6435 and is responsible for the core dmt signal processing), the ad6437 analog front- end ic, the ad816 driver/receiver and adtsp2183, which is used as the system control processor. an object code licence for all modem software is supplied with the ad20msp910 chipset. the AD6435 implements a generic interface, with straightfor- ward synchronous clock and data streams corresponding to simplex and duplex bearer channels. these can be considered as the as0 (simplex) and ls0 (duplex) streams as per the standard, but can run at any rate; the duplex channel can be treated as two independent streams, one up and one down. this implemen- tation is a simplified variant of that described in ansi t1.413. it is easy to use this structure to connect to the rest of the sys- tem, or to external devices, such as framers or dedicated ics for particular protocols. variants of the AD6435 with support for specific functions or interfaces (e.g., atm, ethernet) are under development. there are two main blocks within the AD6435: ? the digital processing section (digital interface area or dia), which is responsible for error correction, scram- bling, interleaving, aoc and control operations. this is based on the earlier ad6442 device. this is a highly pro- grammable system, whose operation is not restricted to the operating modes as defined in ansi t1.413, but which could be used in variety of systems. the dia supports the following codeword cases: a. one codeword per frame in the fact and/or interleaved data portion of a frame. b. multiple codewords per frame in the fast and/or inter- leaved data portion, providing the codeword length evenly divides into the output (dme) frame length. c. multiple frames per codeword on the interleaved portion of the frame only, up to 20 frames per codeword. the number of checkbytes must be an integer multiple of the number of frames in the codeword. d. codewords may span superframes. ? the interface block (transceiver interface and control logic or ticl), which handles the framing, signal buffering and data retim ing functions required to support clean synchro nous data streams. (this essentially corresponds to the transmis sion convergence layer of a stack.) as some designs may not require the ticl block, there is a bypass mode, in which this block is powered down and there is access to the unformatted/unframed data stream from the dia. this data sheet gives a users description of the AD6435. it describes functionality and interfacing, but does not give any details of the internal structure. for details of the internal struc- ture, see the AD6435 users manual, available on request. when used as part of the ad20msp910 adsl chipset, the internal functionality is under the control of the firmware sup- plied with the adtsp2183, and the messaging protocol (mp) implemented there. this protocol supplies a hardware-neutral method of controlling the operation of the adsl chipset, which will be compatible between different hardware implementations. the AD6435 can implement rate adaptive adsl (radsl). this is under the control of the mp, and several different modes are supported. the absolute maximum data rate of the AD6435 is 12 mbps downstream, and 4 mbps upstream. however, the rate depends primarily on the channel conditions, and these rates will not be achieved on real loops, with attenuation and crosstalk. rx_buf rfs rx_fr rx_spfr rx_spfri tx_buf tx_fr tfs tx_spfr mclk_out duplx_rx duplx_clko duplx_clki duplx_tx simplx_clki simplx_tx simplx_clko simplx_rx ncs nwr nrd dsp_clk d(15:0) a(13:0) nreset rt_nco mclk test(4:0) tx_rx_sclk tx_sdata tx_dreq tx_frm tx_bs rx_frm rx_bs rx_sdata rx_dreq m_a(14:0) m_d(7:0) nm_we nm_oe dtir adtsp2183 interface dme interface interleave ram ticl bypass interface data interface control interface figure 1. functional diagram interfaces the standard interface is a very straightforward buffered and demultiplexed synchronous connection. it is physically the same at both atu-r and atu-c, and presents four channels simplex in and out, duplex in and outwith just two signals per connection, clock and data (obviously, only three of these chan- nels can be used at an end; with the atu-c using simplex_in and the atu-r simplex_out). these streams are independent and can be used asynchronously of one another. no framing signals are provided. the duplex stream can be used as a true duplex carrier (same rates upstream and downstream) or the two may be independent (i.e., the chipset has two simplex downstream paths, one fast and one slower, and one simplex upstream).
AD6435 C7C rev. 0 table i. interface descriptions name description duplex_rx duplex data output from the AD6435 (i.e., data received). duplex_clko clock associated with duplex_rx (output). duplex_tx duplex data input to the AD6435 (i.e., data to be transmitted). duplex_clki clock associated with duplex_tx input. simplex_rx simplex data output from the AD6435. atu-r: downstream data received. atu-c: not used. simplex_clko clock associated with simplex_rx (output). simplex_tx sim plex data input to the AD6435. atu-r: not used. atu-c: downstream data to be sent. simplex_clki clock associated with simplex_tx (input). elastic store AD6435 payload data out payload data in driver ad816 driver/receiver ad6436 ad6437 receiver framer eoc remove framer crc crc detect unscramble scrambler fec encode fec decode de-interleaver interleaver ram arbitration ram eoc insert sync tone shuffle constellation encode inverse fft interpolate tone reorder constellation decode fft decimate & tdq dac adc serial dac (to vcxo) control filter filter pga hybrid pots splitter figure 2. ad20msp910 system block diagram in general tx clock signals (i.e., duplex_clcki, simplex_clki) are input to the AD6435, while the received data clock sig- nals (duplex_clko, simplex_clko) are outputs. in other words, the sending modem (at atu-c or atu-r) supplies the clock to the AD6435, and the receiving modems AD6435 recovers it (using a digital phase locked loop) and supplies it to the external system. the channels all have separateindependentclocks. there are two exceptions; the duplex streams can be locked with a single clock or, in a one down/one up system typical for data applications, the unused dpll can be programmed to be a clock source at the desired data rate for the tx channel. to avoid overflow/underflow of internal buffers, the clock rate of the streams should be held roughly constant. as such, al- though a degree of jitter or rate variation is supported, pure burst-mode is not, and idle cell insertion (deletion) is necessary and must be implemented by an external device. alternatively, the buffering multiplex/demultiplex and bit-stuff/ rob operations may be bypassed (ticl bypass operation). these blocks are then powered down, reducing the AD6435s power consumption. the interface presented is then a raw stream of upstream and downstream data. as the elastic store has been disabled, these have the relic of the adsl line super- frame structure, and will show an irregular clock (with a pause for every 69th frame). this mode is compatible with the ad6442 dia interface and is suited to packet (e.g., atm) operation. it results in a slight power saving. nb: although the AD6435 can implement the t1.413 stan- dard, and includes the required framing/interfacing (e.g., elastic store, bit-stuffing/robbing), it does not support the full optional suite of seven bearer streams (asx and lsx) and assoc iated multiplexing/demultiplexing as defined in t1.413. instead, simple synchronous data streams are provided. these are essentially as0 (simplex) and ls0 (duplex) but with vari- able rate or rate adaptive (not merely fixed multiples of standard pdh rates, as per chapter 5 of t1.413). additionally, the du- plex stream can be treated as two independent streams, one up and one down. indeed, in many applications, only one stream in each direction is required; in this case, the downstream duplex path is not used. further tc-layer operations can be defined by the system for their requirements (e.g., for v.35, atm or 10baset), and sim- ply interfaced to the AD6435 serial ports. interface timing the dtir contains simplex (as) and duplex (ls) channels that interface with the central office (co) and remote termi- nal (rt). the dtir contains a transmit serial port in which the dtir transmits a bit stream to the dme and a receive serial port in which dtir receives a serial bit stream from the dme. since the dia is being treated as a black box, the ticl-dia interface will be defined here. this interface is similar to the dia-dme transmit and receive interfaces. the dtir also interfaces with a 32k 8 interleave ram. the dtir also has a dsp host port that allows a dsp to monitor the dtir and control the data through the device.
AD6435 C8C rev. 0 co/rt interface timing simplex serial port the simplex serial port consists of four pins, two outputs, simplx_rx and simplx_clko, and two inputs, simplx_ tx and simplx_clki. the serial clock rate is completely variable between 8 kbps and 12.288 mbps. the interface operates differently at the co and rt locations. simplx_clko simplx_rx dtir xmt rt receive valid data t srx-s t srx-h co xmt dtir receive simplx_clki simplx_tx valid data t stx-s t stx-h figure 3. simplex serial port table ii. tx serial i/f timing parameter description typ t srx-s setup time of simplx_rx from falling edge of simplx_clko 5 ns t srx-h hold time of simplx_rx from falling edge of simplx_clko 5 ns t stx-s setup time of simplx_tx from rising edge of simplx_clki 5 ns t stx-h hold time of simplx_tx from rising edge of simplx_clki 5 ns at the co, the two input pins simplx_tx and simplx_ clki are used while the two output pins simplx_rx and simplx_ clko are not functionally connected. the interface can oper- ate at a continuous data stream into simplx_rx at a fixed frequency between 8 kbps and 12.288 mbps. the data rate is set while the dtir is in reset and does not change without going into the reset state again. at the rt, the two output pins simplx_rx and simplx_ clko are used while the two input pins simplx_tx and simplx_clki are not functionally connected. the interface can operate at a continuous data stream out of simplx_rx at a fixed frequency between 8 kbps and 12.288 mbps. the data rate is set while the dtir is in reset and does not change with- out going into the reset state again. for the simplex rx channel, data is driven out of the AD6435 on the positive edge of the respective clko signal and should be sampled by the external circuit on the negative edge. for the simplex tx channel, the data is sampled by the AD6435 on the positive edge of the respective clko signal and should be driven by the external circuit on the negative edge. duplex serial port the duplex serial port consists of four pins, two outputs, duplx_rx and duplx_clko, and two inputs, duplx_tx and duplx_clki. the serial clock rate is completely variable between 8 kbps and 4.096 mbps. the interface operates identi- cally at the co and rt locations. the input interface can ac- cept a continuous stream of data at a fixed frequency within the duplex rate. the output interface on the other end transmits the same continuous stream of data at the same fixed frequency. this frequency is established and programmed into the registers by the dsp during reset. for the duplex rx channel, data is driven out of the AD6435 on the positive edge of the respective clko signal and should be sampled by the external circuit on the negative edge. for the duplex tx channel, the data is sampled by the AD6435 on the positive edge of the respective clko signal and should be driven by the external circuit on the negative edge. duplx_clko duplx_rx dtir xmt co/rt receive valid data t drx-s t drx-h co/rt xmt dtir receive duplx_clki duplx_tx valid data t dtx-s t dtx-h figure 4. duplex serial port table iii. tx serial i/f timing parameter description typ t drx-s setup time of duplx_rx from falling edge of duplx_clko 5 ns t drx-h hold time of duplx_rx from falling edge of duplx_clko 5 ns t dtx-s setup time of duplx_tx from rising edge of duplx_clki 5 ns t dtx-h hold time of duplx_tx from rising edge of duplx_clki 5 ns interleave ram interface the dtir (dia) interfaces an external 32k 8 interleave ram. the interleave ram interface consists of m_a(14:0), m_d(7:0), nm_we, and nm_oe. when operating at 3.3 v ram must have access time less than 50 ns. for further infor- mation concerning the operation of the ram access, consult the dia specification. dme interface timing all signals transmitted by the dme to the dtir are transmit- ted on the rising edge and sampled on the falling edge except for the tx_dreq signal that is transmitted by the dme on the falling edge and sampled by the dtir on the rising edge. all output signals from the dtir to the dme are transmitted by the dtir on the rising edge and received by the dme on the rising edge.
AD6435 C9C rev. 0 parameter description typ units tx serial i/f timing t tfrm-s setup time of tx_frm from falling edge of tx_rx_sclk 5 ns t tfrm-h hold time of tx_frm from falling edge of tx_rx_sclk 15 ns t tdreq-s setup time of tx_dreq from rising edge of tx_rx_sclk 5 ns t tdreq-h hold time of tx_dreq from rising edge of tx_rx_sclk 15 ns t tbs-s setup time of tx_bs from rising edge of tx_rx_sclk 10 ns t tbs-h hold time of tx_bs from rising edge of tx_rx_sclk 0 ns t td_s setup time of tx_sdata from rising edge of tx_rx_sclk 5 ns t td_h hold time of tx_sdata from rising edge of tx_rx_sclk 0 ns valid data t td-s t td-h t tbs-s t tbs-h t tfrm-s t tfrm-h t tdreq-s t tdreq-h tx_rx_sclk tx_frm tx_dreq tx_bs tx_sdata figure 5. tx serial i/f timing parameter description typ units rx serial i/f timing t rfrm-s setup time of rx_frm from falling edge of tx_rx_sclk 5 ns t rfrm-h hold time of rx_frm from falling edge of tx_rx_sclk 15 ns t rdreq-s setup time of rx_dreq from rising edge of tx_rx_sclk 5 ns t rdreq-h hold time of rx_dreq from rising edge of tx_rx_sclk 0 ns t rbs-s setup time of rx_bs from falling edge of tx_rx_sclk 5 ns t rbs-h hold time of rx_bs from falling edge of tx_rx_sclk 15 ns t rd-s setup time of rx_sdata from falling edge of tx_rx_sclk 5 ns t rd-h hold time of rx_sdata from falling edge of tx_rx_sclk 15 ns valid data t rd-s t rd-h t rbs-s t rbs-h t rfrm-s t rfrm-h t rdreq-s t rdreq-h tx_rx_sclk rx_frm rx_dreq rx_bs rx_sdata figure 6. rx serial i/f timing
AD6435 C10C rev. 0 tx serial port the tx serial interface between the dme and dtir uses five (5) signals: tx_rx_sclk: serial clock provided by dme. tx_dreq: data request provided by dme. tx_frm: frame strobe provided by dme. tx_bs: byte strobe provided by dtir. tx_sdata: serial data provided by dtir. rx serial interface the rx serial interface between the dme and dtir uses five (5) signals: tx_rx_sclk: serial clock provided by dme. rx_frmrx_frm: frame strobe provided by dme. rx_bs: byte strobe provided by dme. rx_sdata: serial data provided by dme. rx_dreq: data request provided by dtir. dsp port the dsp port consists of a 14-bit address bus, a[13:0], a 16-bit data bus, d[15:0], dsp_clk and three bus control pins, nrd, nwr, ncs. parameter min max unit read operation timing requirements : t rdd nrd low to data valid 8 ns t aa a0Ca13, ncs to data valid 14 ns t rdh data hold from nrd high 0 ns switching characteristics: t rp nrd pulsewidth 12 ns t crd dsp_clk high to nrd low 3 16 ns t asr a0Ca13, ncs setup before nrd low 2 ns t rda a0Ca13, ncs hold after nrd deasserted 5 ns t rwr nrd high to nrd or nwr low 12 ns note: dsp clock 28 mhz (35.7 ns) t rdd t rdh dsp_clk a0Ca13 d t rda t rwr t rp t asr t crd t aa nrd nwr ncs figure 7. read operation
AD6435 C11C rev. 0 parameter min max unit write operation switching characteristics : t dw data setup before nwr high 10 ns t dh data hold after nwr high 6 ns t wp nwr pulsewidth 12 ns t wde nwr low to data enabled 0 ns t asw a0Ca13, ncs setup before nwr low 2 ns t ddr data disable before nwr or nrd low 1 ns t cwr dsp_clk high to nwr low 3 16 ns t aw a0Ca13, ncs, setup before nwr deasserted 17 ns t wra a0Ca13, ncs hold after nwr deasserted 5 ns t wwr nwr high to nrd or nwr low 12 ns note: dsp clock 28 mhz (35.7 ns) dsp_clk a0Ca13 d t wp t aw t cwr t dh t wde t dw t asw t wwr t wra t ddr ncs nrd nwr figure 8. write operation
C12C c3227C3C10/97 printed in u.s.a. AD6435 rev. 0 outline dimensions dimensions shown in inches and (mm). 128-lead plastic thin quad flatpack (st-128) top view (pins down) 1 38 39 65 64 102 128 103 0.011 (0.27) 0.009 (0.22) 0.007 (0.17) 0.551 (14.00) bsc 0.630 (16.00) bsc 0.866 (22.00) bsc 0.787 (20.00) bsc 0.020 (0.50) bsc seating plane 0.063 (1.60) typ 0.030 (0.75) 0.024 (0.60) 0.018 (0.45) 0.003 (0.08) max 0.006 (0.15) 0.002 (0.05) 0.057 (1.45) 0.053 (1.40) 0.018 (1.35)

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